(1) Field of the Invention
The invention relates to designing and verifying an integrated circuit device with multiple power domains, and more particularly, to a method and an apparatus for automatically placing and routing and then verifying a multi-power IC device.
(2) Description of the Prior Art
As deep sub-micron ASIC and IC technology evolves, integrated circuit devices are being designed and fabricated with digital blocks, analog blocks, and embedded memories on single chips. Such combinational IC devices are commonly called multi-power devices. In multi-power devices, it is well known that the digital circuits typically occupy the majority of the die area (typically more than 70%). These digital circuits have fast switching speeds and therefore generate a great deal of switching noise on the digital power supply. This noisy digital power is generally not acceptable for use in the analog circuits co-resident on the chip. Therefore, a separate analog power must be provided.
Referring now to FIG. 1, a typical mixed-mode integrated circuit device 10 is illustrated. In this device 10, a digital block 14 and an analog block 18 are co-resident. The digital circuit 14 comprises typical combinational logic gates and registers. The digital circuit physical view or layout may be generated using automatic place and route software that automatically selects standard digital layout cells from a library, places these cell into the layout, and then routes conductive lines to each standard cell. The digital block 14 has a set of input and output (I/O) pins 22 to provide connectivity outside the IC device 10.
The analog block 18 comprises the analog circuitry designed onto the IC device 10. For example, analog-to-digital converters or operational amplifiers may be integrated in the analog block 18. While the analog block may be automatically placed and routed, often, these circuits must be individually drawn using a computer-aided design (CAD) system to insure that performance specifications are achieved. However, the automated place and route software may still place and route the completed analog block 18 into the IC device layout 10. The analog block 18 has a set of I/O pins 26 that provide external connectivity.
The particular requirements of the example IC device 10 dictate the use of several power supplies. For example, the digital circuit 14 is powered by the VDD1 38 line and return ground VSS 30. As discussed above, the high speed switching capabilities of the digital circuit 14 tends to make the digital circuit power supply, VDD1 38, very noisy. That is, switching noise is coupled onto the dc voltage level of the power supply. Therefore, the analog circuit 18 is powered using a separate analog power supply VCC 34. Additionally, the digital power supply VDD1 38 and the analog power supply VCC 34 may comprise different voltage values.
In addition to the need to split the analog and digital supplies, there is an additional need for creating multiple power supplies or multi-power domains. The output pin 62 for the digital block 14 contains a pre-driver or low voltage (LV) portion 54 and a post-driver or high voltage (HV) portion 58. For example, the low voltage 54 portion and high voltage portion 58 may comprise a level-shifter circuit that is needed for shifting the internal voltage level of the digital circuit 14 up to a higher voltage used in the external system. In this case, the low voltage portion 54 of the output pin is powered by the VDD2 supply 42 while the high voltage portion 58 is powered by the VDD3 supply 46. For example, the VDD2 supply 42 may comprise a voltage of about 2.5 Volts and the VDD3 supply 46 may comprise a voltage of about 3.3 Volts.
These power supply signals 34, 38, 42, and 46 may be routed in a power cut cell 50. This power cut cell 50 is connected to the main power supply in normal operation. The power cut cell 50 comprises a number of diodes, not shown, between the two power rails to thereby provide separation between the various power domains on the IC device while also providing electrostatic discharge (ESD) protection paths. Further, more than one power cut cell 50 may be used on the IC device, as needs dictate. As will be seen, the use of these power cut cells 50 causes special problems when automated placement and routing software are used to design and layout these multi-power IC devices.
Referring now to FIG. 2, a flow chart of key steps in an integrated circuit design and verification method is illustrated. In a typical IC design, a gate-level netlist is generated as shown in step 100. This gate-level netlist is typically generated by a logic synthesis tool. Frequently, the design of the analog and digital blocks of the multi-power device are performed by separate engineers or engineering teams. The circuits are simulated on the CAE workstation tool to verify their performance against the design specification or perhaps against a high-level model.
A typical scenario for the design process involves significant segmentation of the design task. For example, it is a frequent occurrence in the art for one company, in this case referred to as the customer, to design an integrated circuit device and perform verification simulations at the gate-level. Once the first company is satisfied with the correctness of the circuit design, the design netlist is handed off to a second company where the design is converted to a physical view or layout sufficient for the creation of photolithographic reticles. These reticles, or masks, are then used, perhaps by yet a third company, to fabricate the integrated circuit devices in a wafer fabrication facility.
It is important to note that, at this point in the process, the gate-level netlist file 100 typically does not contain multi-power nets. This is because the typical gate-level simulation tools, such as are used for simulating the digital block, are capable of only binary simulations. Pre-simulation and post-simulation analysis is carried out by the customer on the gate-level netlist without the multi-power information or nets in step 104. Further, static timing analysis (STA) is completed using the gate-level netlist without multi-power nets in step 108. The customer evaluates the results of the simulations and analysis of steps 104 and 108 to verify the correctness of the design in step 112. If further refinements are warranted, the schematic and netlist are updated in step 118 to generate a new netlist for further simulation and analysis. Once the design is deemed correct in step 112, the customer is able to release the gate-level netlist 100 in step 116. Once again, this netlist does not contain the multi-power net information that would be needed to fully verify a completed physical layer.
Referring now to FIG. 3, the customer gate-level netlist 120 without multi-power nets is brought into the company where the physical view or layout steps will be performed. This gate-level netlist 120 is imported into a placement and routing software system in step 124. The placement and routing software will parse the gate-level netlist and select all of the standard logic cell components needed for the design. These standard logic cells will then be placed in an array in the area of the IC layout designated for the logic section. Finally, a conductive line layer will be automatically routed to connect each standard cell in the array to the appropriate inputs and outputs.
Note that several special techniques must be used in this placement and routing sequence to compensate for the use of multiple power domains on the design. First, the netlist must be manually edited to attach a “:” to each of the power net references the first placement and routing step 124. This will cause all of the power nets to be recognized as ‘virtually shorted’ by the placement and routing software. Once the first placement and routing pass is completed in step 124, a physical view or layout is generated in GDS format as output 128.
At this point, a first layout versus schematic verification (LVS) is performed in step 132. Note that this LVS step 132 is performed using the original customer gate-level netlist 120 without multi-power nets. After the physical view output 128 is verified by the LVS step 132, a second placement and routing operation is performed in step 134. In the second placement and routing operation 134, the text labeling is added to the top view layout. Particular conductive lines and nodes are thereby labeled as belonging to particular power domains in the multi-power scheme and the power domains are separated. The second placement and routing operation of step 134 generates the second physical view output 138.
The second physical view output 138 is now ready for LVS. However, the customer gate-level netlist 120 must now be revised to add all of the multi-power net information in step 142. The revised netlist is thereby generated 144. Finally, the second physical view 138 is verified by a LVS check against the revised netlist 144 to complete an LVS verification with multi-power nets in step 146.
Notice that the original customer gate-level netlist 120 has been altered in two ways. First, in step 124, the original netlist 120 was manually altered to add the “:” to allow the placement and routing software to work. Second, the original netlist 120 was altered to add the multi-power nets into the netlist in step 142. Each step of alteration is risky for the second company to undertake. Any deviation in the original netlist 120 received from the customer could cause an error to be introduced that the customer is unaware of. Further, the customer has no opportunity to simulate or analyze the altered netlist to thereby detect errors using the customer's design tools. Finally, the process sequence forces the company performing the IC device layout to perform two, separate passes of placement and routing and LVS verification. This extra processing ties up very expensive human and computing resources.
Several prior art inventions describe multi-power devices and integrated circuit design methods and tools. U.S. Pat. No. 6,043,128 to Kamiya teaches a method to form a semiconductor device capable of handling multiple power sources. Specifically, the method teaches the fabrication of MOS transistors with differing gate oxide thicknesses. U.S. Pat. No. 5,084,824 to Lam et al discloses a method and an apparatus for generating a gate-level netlist for an integrated circuit macrocell. The gate-level netlist is suitable for use in a simulation model and is derived from the physical layout of the macrocell. U.S. Pat. No. 5,666,288 to Jones et al teaches a method and an apparatus for designing an integrated circuit. A behavioral model and an initial logic cell library are provided to a design synthesis tool. This design synthesis tool processes these inputs to create a gate-level schematic netlist. Further processing redefines cell boundaries, transistor sizes, power rails, and cell pitches and heights to thereby optimize the design. A new hybrid cell library is then created based on these optimizations. This new hybrid cell library is then used for automatic placement and routing. U.S. Pat. No. 5,812,416 to Gupte et al teaches a method and an apparatus for automatically generating synthesis scripts and hierarchical flow connectivity diagrams for use in an integrated circuit design. U.S. Pat. No. 5,903,475 to Gupte et al discloses a method and an apparatus to verify an ASIC design using a test bench module.